Jens Krüger

Filippo Mantovani, Fabio Banchelli, Pablo Vizcaino et al.

This paper presents EPAC, a RISC-V-based accelerator chip developed within the European Processor Initiative (EPI) as part of a multi-year, multi-partner effort to build a European HPC processor ecosystem. EPAC is implemented in GlobalFoundries 22FDX (GF22FDX) technology, covers an area of 27 sq mm with approximately 0.3 billion transistors, and integrates three distinct RISC-V compute tiles targeting different workload classes: VEC, a vector processing tile for double-precision HPC workloads; STX, a many-core tile optimized for stencil and machine learning computations; and VRP, a variable-precision tile for iterative numerical solvers requiring extended floating-point formats. All tiles are connected through a Coherent Hub Interface (CHI) based network-on-chip with a distributed L2 cache system and communicate with external memory via a SerDes link. The chip was taped out in GF22FDX technology and successfully brought up, with all major IP blocks validated. This paper describes the architecture of each tile and the uncore infrastructure, the integration and physical implementation process, and the board-level bring-up activities. It also reflects on the engineering and coordination lessons learned from a full chip design effort distributed across academic and industrial partners in Europe.

Jonas Ney, Dominik Loroch, Vladimir Rybalkin et al.

Deep Neural Networks (DNNs) are capable of solving complex problems in domains related to embedded systems, such as image and natural language processing. To efficiently implement DNNs on a specific FPGA platform for a given cost criterion, e.g. energy efficiency, an enormous amount of design parameters has to be considered from the topology down to the final hardware implementation. Interdependencies between the different design layers have to be taken into account and explored efficiently, making it hardly possible to find optimized solutions manually. An automatic, holistic design approach can improve the quality of DNN implementations on FPGA significantly. To this end, we present a cross-layer design space exploration methodology. It comprises optimizations starting from a hardware-aware topology search for DNNs down to the final optimized implementation for a given FPGA platform. The methodology is implemented in our Holistic Auto machine Learning for FPGAs (HALF) framework, which combines an evolutionary search algorithm, various optimization steps and a library of parametrizable hardware DNN modules. HALF automates both the exploration process and the implementation of optimized solutions on a target FPGA platform for various applications. We demonstrate the performance of HALF on a medical use case for arrhythmia detection for three different design goals, i.e. low-energy, low-power and high-throughput respectively. Our FPGA implementation outperforms a TensorRT optimized model on an Nvidia Jetson platform in both throughput and energy consumption.

Andrey Krekhov, Daniel Preuß, Sebastian Cmentowski et al.

Watching others play is a key ingredient of digital games and an important aspect of games user research. However, spectatorship is not very popular in virtual reality, as such games strongly rely on one's feelings of presence. In other words, the head-mounted display creates a barrier between the player and the audience. We contribute an alternative watching approach consisting of two major components: a dynamic view frustum that renders the game scene from the current spectator position and a one-way mirror in front of the screen. This mirror, together with our silhouetting algorithm, allows seeing the player's reflection at the correct position in the virtual world. An exploratory survey emphasizes the overall positive experience of the viewers in our setup. In particular, the participants enjoyed their ability to explore the virtual surrounding via physical repositioning and to observe the blended player during object manipulations. Apart from requesting a larger screen, the participants expressed a strong need to interact with the player. Consequently, we suggest utilizing our technology as a foundation for novel playful experiences with the overarching goal to transform the passive spectator into a collocated player.