Dharanidhar Dang

Md Rahatul Islam Udoy, Dharanidhar Dang, Wantong Li et al.

This paper presents ThermoPix, a CMOS-compatible electronic-photonic architecture for high-spatial-resolution temperature sensing. The proposed system converts temperature-induced wavelength shifts in a photonic interferometric sensor into timing information that can be processed by CMOS circuitry. We use a valley photonic crystal Mach-Zehnder interferometer (VPCMZI) as the sensing element, whose temperature-dependent spectral response is detected using an integrated waveguide photodetector and translated into a time-varying photocurrent. A CMOS readout circuit employing a phase-transition-material device performs threshold detection and generates a timing signal corresponding to the temperature-dependent crossing event. Circuit-level simulations demonstrate a temperature sensitivity of 3.15 ns/K, a row readout time of 2 us, and a sensing power-delay product (PDP) of 0.152 fJ. The required optical power per photonic cell is 150 nW, enabling energy-efficient array operation without requiring cooling or special environmental arrangements. We also present alternative photonic layer architectures for optical power distribution across the array. In one approach, we use different tap ratios along the row, while the other uses identical tap ratios with bidirectional excitation. The resulting average photonic cell pitches are 23.26 um and 38.52 um, respectively. The proposed ThermoPix architecture therefore provides a scalable platform for integrated temperature sensing arrays that combine photonic sensing elements with CMOS-compatible timing-based readout.

Dharanidhar Dang, Amitash Nanda, Bill Lin et al.

With Moore's law saturating and Dennard scaling hitting its wall, traditional Von Neuman systems cannot offer the GFlops/watt for compute-intensive algorithms such as CNN. Recent trends in unconventional computing approaches give us hope to design highly energy-efficient computing systems for such algorithms. Neuromorphic computing is a promising such approach with its brain-inspired circuitry, use of emerging technologies, and low-power nature. Researchers use a variety of novel technologies such as memristors, silicon photonics, FinFET, and carbon nanotubes to demonstrate a neuromorphic computer. However, a flexible CAD tool to start from neuromorphic logic design and go up to architectural simulation is yet to be demonstrated to support the rise of this promising paradigm. In this project, we aim to build NeuCASL, an opensource python-based full system CAD framework for neuromorphic logic design, circuit simulation, and system performance and reliability estimation. This is a first of its kind to the best of our knowledge.

Dharanidhar Dang, Bill Lin, Debashis Sahoo

Deep learning is highly pervasive in today's data-intensive era. In particular, convolutional neural networks (CNNs) are being widely adopted in a variety of fields for superior accuracy. However, computing deep CNNs on traditional CPUs and GPUs brings several performance and energy pitfalls. Several novel approaches based on ASIC, FPGA, and resistive-memory devices have been recently demonstrated with promising results. Most of them target only the inference (testing) phase of deep learning. There have been very limited attempts to design a full-fledged deep learning accelerator capable of both training and inference. It is due to the highly compute and memory-intensive nature of the training phase. In this paper, we propose LiteCON, a novel analog photonics CNN accelerator. LiteCON uses silicon microdisk-based convolution, memristor-based memory, and dense-wavelength-division-multiplexing for energy-efficient and ultrafast deep learning. We evaluate LiteCON using a commercial CAD framework (IPKISS) on deep learning benchmark models including LeNet and VGG-Net. Compared to the state-of-the-art, LiteCON improves the CNN throughput, energy efficiency, and computational efficiency by up to 32x, 37x, and 5x respectively with trivial accuracy degradation.