Ahmedullah Aziz

Md Mazharul Islam, Shamiul Alam, Md Shafayat Hossain et al.

The revolution in artificial intelligence (AI) brings up an enormous storage and data processing requirement. Large power consumption and hardware overhead have become the main challenges for building next-generation AI hardware. To mitigate this, Neuromorphic computing has drawn immense attention due to its excellent capability for data processing with very low power consumption. While relentless research has been underway for years to minimize the power consumption in neuromorphic hardware, we are still a long way off from reaching the energy efficiency of the human brain. Furthermore, design complexity and process variation hinder the large-scale implementation of current neuromorphic platforms. Recently, the concept of implementing neuromorphic computing systems in cryogenic temperature has garnered intense interest thanks to their excellent speed and power metric. Several cryogenic devices can be engineered to work as neuromorphic primitives with ultra-low demand for power. Here we comprehensively review the cryogenic neuromorphic hardware. We classify the existing cryogenic neuromorphic hardware into several hierarchical categories and sketch a comparative analysis based on key performance metrics. Our analysis concisely describes the operation of the associated circuit topology and outlines the advantages and challenges encountered by the state-of-the-art technology platforms. Finally, we provide insights to circumvent these challenges for the future progression of research.

Md Rahatul Islam Udoy, Dharanidhar Dang, Wantong Li et al.

This paper presents ThermoPix, a CMOS-compatible electronic-photonic architecture for high-spatial-resolution temperature sensing. The proposed system converts temperature-induced wavelength shifts in a photonic interferometric sensor into timing information that can be processed by CMOS circuitry. We use a valley photonic crystal Mach-Zehnder interferometer (VPCMZI) as the sensing element, whose temperature-dependent spectral response is detected using an integrated waveguide photodetector and translated into a time-varying photocurrent. A CMOS readout circuit employing a phase-transition-material device performs threshold detection and generates a timing signal corresponding to the temperature-dependent crossing event. Circuit-level simulations demonstrate a temperature sensitivity of 3.15 ns/K, a row readout time of 2 us, and a sensing power-delay product (PDP) of 0.152 fJ. The required optical power per photonic cell is 150 nW, enabling energy-efficient array operation without requiring cooling or special environmental arrangements. We also present alternative photonic layer architectures for optical power distribution across the array. In one approach, we use different tap ratios along the row, while the other uses identical tap ratios with bidirectional excitation. The resulting average photonic cell pitches are 23.26 um and 38.52 um, respectively. The proposed ThermoPix architecture therefore provides a scalable platform for integrated temperature sensing arrays that combine photonic sensing elements with CMOS-compatible timing-based readout.

Jack Hutchins, Shamiul Alam, Dana S. Rampini et al.

The relentless pursuit of miniaturization and performance enhancement in electronic devices has led to a fundamental challenge in the field of circuit design and simulation: how to accurately account for the inherent stochastic nature of certain devices. While conventional deterministic models have served as indispensable tools for circuit designers, they fall short when it comes to capture the subtle yet critical variability exhibited by many electronic components. In this paper, we present an innovative approach that transcends the limitations of traditional modeling techniques by harnessing the power of machine learning, specifically Mixture Density Networks (MDNs), to faithfully represent and simulate the stochastic behavior of electronic devices. We demonstrate our approach to model heater cryotrons, where the model is able to capture the stochastic switching dynamics observed in the experiment. Our model shows 0.82% mean absolute error for switching probability. This paper marks a significant step forward in the quest for accurate and versatile compact models, poised to drive innovation in the realm of electronic circuits.

Md Rahatul Islam Udoy, Diego Ferrer, Wantong Li et al.

Ensuring end-to-end security in image sensors has become essential as visual data can be exposed through multiple stages of the imaging pipeline. Advanced protection requires encryption to occur before pixel values appear on any readout lines. This work introduces a secure pixel sensor (SecurePix), a compact CMOS-compatible pixel architecture that performs true in-pixel encryption using a symmetric key realized through programmable, non-volatile multidomain polarization states of a ferroelectric field-effect transistor. The pixel and array operations are designed and simulated in HSPICE, while a 45 nm CMOS process design kit is used for layout drawing. The resulting layout confirms a pixel pitch of 2.33 x 3.01 um^2. Each pixel's non-volatile programming level defines its analog transfer characteristic, enabling the photodiode voltage to be converted into an encrypted analog output within the pixel. Full-image evaluation shows that ResNet-18 recognition accuracy drops from 99.29 percent to 9.58 percent on MNIST and from 91.33 percent to 6.98 percent on CIFAR-10 after encryption, indicating strong resistance to neural-network-based inference. Lookup-table-based inverse mapping enables recovery for authorized receivers using the same symmetric key. Based on HSPICE simulation, the SecurePix achieves a per-pixel programming power-delay product of 17 uW us and a per-pixel sensing power-delay product of 1.25 uW us, demonstrating low-overhead hardware-level protection.

Baibhari Priya Barua, Md Rahatul Islam Udoy, Ahmedullah Aziz

Thermal behavior has become a first-order constraint in advanced 2.5D/3D integrated circuits (ICs) and heterogeneous packages. As power densities rise and multiple active dies are vertically integrated, heat removal paths become constricted, elevating junction temperatures, magnifying temperature gradients, and exacerbating reliability risks. This review synthesizes the physical mechanisms, modeling assumptions, and analysis methods that govern multiscale thermal transport in 3D ICs, with emphasis on interface-dominated conduction, material anisotropy, and strong electrothermal coupling. We unify device-to-system scales into a coherent framework, analyzing trade-offs among compact thermal models (CTMs), finite element/finite difference methods (FEM/FDM), Green's function and semi-analytical techniques, reduced-order and multi-fidelity methods, and physics-informed machine learning (PIML), while highlighting the central role of thermal boundary resistance (TBR) and variability in thermal interface materials (TIMs), the pitfalls of decoupled electrical/thermal analyses, and the need for rigorous validation against measurements. Finally, we outline practical design guidelines and a forward-looking research agenda that integrates physics-based modeling, data-driven surrogates, and in situ sensing to enable thermally aware co-optimization across the IC-package-system hierarchy.

Md Rahatul Islam Udoy, Shamiul Alam, Md Mazharul Islam et al.

Digital pixel sensor (DPS) has evolved as a pivotal component in modern imaging systems and has the potential to revolutionize various fields such as medical imaging, astronomy, surveillance, IoT devices, etc. Compared to analog pixel sensors, the DPS offers high speed and good image quality. However, the introduced intrinsic complexity within each pixel, primarily attributed to the accommodation of the ADC circuit, engenders a substantial increase in the pixel pitch. Unfortunately, such a pronounced escalation in pixel pitch drastically undermines the feasibility of achieving high-density integration, which is an obstacle that significantly narrows down the field of potential applications. Nonetheless, designing compact conversion circuits along with strategic integration of 3D architectural paradigms can be a potential remedy to the prevailing situation. This review article presents a comprehensive overview of the vast area of DPS technology. The operating principles, advantages, and challenges of different types of DPS circuits have been analyzed. We categorize the schemes into several categories based on ADC operation. A comparative study based on different performance metrics has also been showcased for a well-rounded understanding.

Md Rahatul Islam Udoy, Md Mazharul Islam, Elijah Johnson et al.

This paper presents an innovative in-pixel contrast enhancement circuit that performs image processing directly within the pixel circuit. The circuit can be tuned for different modes of operation. In foreground enhancement mode, it suppresses low-intensity background pixels to nearly zero, isolating the foreground for better object visibility. In contrast enhancement mode, it improves overall image contrast. The contrast enhancement function is customizable both during the design phase and in real-time, allowing the circuit to adapt to specific applications and varying lighting conditions. A model of the designed pixel circuit is developed and applied to a full pixel array, demonstrating significant improvements in image quality. Simulations performed in HSPICE show a nearly 6x increase in Michelson Contrast Ratio (CR) in the foreground enhancement mode. The simulation results indicate its potential for real-time, adaptive contrast enhancement across various imaging environments.

Tasnia Nobi Afee, Jack Hutchins, Md Mazharul Islam et al.

FeFETs hold strong potential for advancing memory and logic technologies, but their inherent randomness arising from both operational cycling and fabrication variability poses significant challenges for accurate and reliable modeling. Capturing this variability is critical, as it enables designers to predict behavior, optimize performance, and ensure reliability and robustness against variations in manufacturing and operating conditions. Existing deterministic and machine learning-based compact models often fail to capture the full extent of this variability or lack the mathematical smoothness required for stable circuit-level integration. In this work, we present an enhanced probabilistic modeling framework for FeFETs that addresses these limitations. Building upon a Mixture Density Network (MDN) foundation, our approach integrates C-infinity continuous activation functions for smooth, stable learning and a device-specific embedding layer to capture intrinsic physical variability across devices. Sampling from the learned embedding distribution enables the generation of synthetic device instances for variability-aware simulation. With an R2 of 0.92, the model demonstrates high accuracy in capturing the variability of FeFET current behavior. Altogether, this framework provides a scalable, data-driven solution for modeling the full stochastic behavior of FeFETs and offers a strong foundation for future compact model development and circuit simulation integration.

Shamiul Alam, Md Shafayat Hossain, Ahmedullah Aziz

Controlling the spread of infectious diseases, such as the ongoing SARS-CoV-2 pandemic, is one of the most challenging problems for human civilization. The world is more populous and connected than ever before, and therefore, the rate of contagion for such diseases often becomes stupendous. The development and distribution of testing kits cannot keep up with the demand, making it impossible to test everyone. The next best option is to identify and isolate the people who come in close contact with an infected person. However, this apparently simple process, commonly known as - contact tracing, suffers from two major pitfalls: the requirement of a large amount of manpower to track the infected individuals manually and the breach in privacy and security while automating the process. Here, we propose a Bluetooth based contact tracing hardware with anonymous IDs to solve both the drawbacks of the existing approaches. The hardware will be a wearable device that every user can carry conveniently. This device will measure the distance between two users and exchange the IDs anonymously in the case of a close encounter. The anonymous IDs stored in the device of any newly infected individual will be used to trace the risky contacts and the status of the IDs will be updated consequently by authorized personnel. To demonstrate the concept, we simulate the working procedure and highlight the effectiveness of our technique to curb the spread of any contagious disease.