Zhixiong Di

Zhixiong Di, Runzhe Tao, Lin Chen et al. · pku

Packing is a required step in a typical FPGA CAD flow. It has high impacts to the performance of FPGA placement and routing. Early prediction of packing results can guide design optimization and expedite design closure. In this work, we propose an imbalanced large graph learning framework, ImLG, for prediction of whether logic elements will be packed after placement. Specifically, we propose dedicated feature extraction and feature aggregation methods to enhance the node representation learning of circuit graphs. With imbalanced distribution of packed and unpacked logic elements, we further propose techniques such as graph oversampling and mini-batch training for this imbalanced learning task in large circuit graphs. Experimental results demonstrate that our framework can improve the F1 score by 42.82% compared to the most recent Gaussian-based prediction method. Physical design results show that the proposed method can assist the placer in improving routed wirelength by 0.93% and SLICE occupation by 0.89%.

Xiao Yan, Zhixiong Di, Bowen Huang et al.

Although it has been surpassed by many subsequent coding standards, JPEG occupies a large share of the storage load of the current data hosting service. To reduce the storage costs, DropBox proposed a lossless secondary compression algorithm, Lepton, to further improve the compression rate of JPEG images. However, the bloated probability models defined by Lepton severely restrict its throughput and energy efficiency. To solve this problem, we construct an efficient access probability-based hash function for the probability models, and then propose a hardware-friendly memory optimization method by combining the proposed hash function and the N-way Set-Associative unit. After that, we design a highly parameterized hardware structure for the probability models and finally implement a power and area efficient Lepton hardware encoder. To the best of our knowledge, this is the first hardware implementation of Lepton. The synthesis result shows that the proposed hardware structure reduces the total area of the probability models by 70.97%. Compared with DropBox's software solution, the throughput and the energy efficiency of the proposed Lepton hardware encoder are increased by 55.25 and 4899 times respectively. In terms of manufacturing cost, the proposed Lepton hardware encoder is also significantly lower than the general-purpose CPU used by DropBox.