Jeffry Victor

Jeffry Victor, Chunguang Wang, Sumeet K. Gupta

Crossbar memory arrays have been touted as the workhorse of in-memory computing (IMC)-based acceleration of Deep Neural Networks (DNNs), but the associated hardware non-idealities limit their efficacy. To address this, cross-layer design solutions that reduce the impact of hardware non-idealities on DNN accuracy are needed. In Part 1 of this paper, we established the co-optimization strategies for various memory technologies and their crossbar arrays, and conducted a comparative technology evaluation in the context of IMC robustness. In this part, we analyze various design knobs such as array size and bit-slice (number of bits per device) and their impact on the performance of 8T SRAM, ferroelectric transistor (FeFET), Resistive RAM (ReRAM) and spin-orbit-torque magnetic RAM (SOT-MRAM) in the context of inference accuracy at 7nm technology node. Further, we study the effect of circuit design solutions such as Partial Wordline Activation (PWA) and custom ADC reference levels that reduce the hardware non-idealities and comparatively analyze the response of each technology to such accuracy enhancing techniques. Our results on ResNet-20 (with CIFAR-10) show that PWA increases accuracy by up to 32.56% while custom ADC reference levels yield up to 31.62% accuracy enhancement. We observe that compared to the other technologies, FeFET, by virtue of its small layout height and high distinguishability of its memory states, is best suited for large arrays. For higher bit-slices and a more complex dataset (ResNet-50 with Cifar-100) we found that ReRAM matches the performance of FeFET.

Jeffry Victor, Dong Eun Kim, Chunguang Wang et al.

Deep neural network (DNN) accelerators employing crossbar arrays capable of in-memory computing (IMC) are highly promising for neural computing platforms. However, in deeply scaled technologies, interconnect resistance severely impairs IMC robustness, leading to a drop in the system accuracy. To address this problem, we propose SWANN - a technique based on shuffling weights in crossbar arrays which alleviates the detrimental effect of wire resistance on IMC. For 8T-SRAM-based 128x128 crossbar arrays in 7nm technology, SWANN enhances the accuracy from 47.78% to 83.5% for ResNet-20/CIFAR-10. We also show that SWANN can be used synergistically with Partial-Word-LineActivation, further boosting the accuracy. Moreover, we evaluate the implications of SWANN for compact ferroelectric-transistorbased crossbar arrays. SWANN incurs minimal hardware overhead, with less than a 1% increase in energy consumption. Additionally, the latency and area overheads of SWANN are ~1% and ~16%, respectively when 1 ADC is utilized per crossbar array.

Jeffry Victor, Sumeet K. Gupta

Piezoelectric FET (PeFET) is a promising non-volatile-memory (NVM) device that integrates a piezoelectric (PE)/ferroelectric (FE) capacitor with a 2D transistor. It uses the polarization of the FE capacitor for bit-storage and strain-induced bandgap change of the 2D channel during read. Previous PeFET-based NVM designs have shown immense promise in achieving high density and energy-efficiency compared to SRAM. However, a key limitation of these designs is that they must trade-off integration density to enhance energy-efficiency or augment the memory functionality with in-memory computing (IMC). In this work, we show that the unique structure of the PeFET presents an appealing opportunity to counter these limitations, thereby simultaneously achieving high density, high energy-efficiency, and IMC-compatibility. First, we highlight the key reasons for the limited energy-efficiency of the previous PeFET designs. Based on these insights, we propose two flavors of PeFET memories that utilize negative voltage (NeVo) to reduce the major energy-consuming components significantly. Compared to 6T-SRAM (prior PeFET-based NVMs), the proposed designs achieve substantial reductions in energy, lowering read energy to 0.08x(0.03x) and write energy to 0.19x(0.53x), respectively. We then leverage these cells to implement IMC primitives, such as addition, subtraction, and multiply-and-accumulate (MAC), achieving 0.03x the energy consumption of prior PeFET-based designs.