Naoki Matsumoto

Akihiro Higashitani, Diogo Kendy Matsumoto, Naoki Matsumoto

In this paper, we consider triangle-free graphs with diameter 2. If a triangle-free graph $G$ with diameter 2 is not isomorphic to a star, then the radius of $G$ is also 2, where such a graph is also called a $2$-self-centered graph. Shekarriz et al. [A characterization for 2-self-centered graphs, Discuss. Math. Graph Theory 38 (2018), 27--37.] gave a characterization of 2-self-centered graphs. However, there is a slight flaw in their characterization. Thus, in this paper, we modify it and prove an accurate characterization of those graphs. Furthermore, by using our characterization, we prove some results concerning the chromatic number of triangle-free graphs with diameter 2.

Kotaro Matsuoka, Ryotaro Banno, Naoki Matsumoto et al.

We present Virtual Secure Platform (VSP), the first comprehensive platform that implements a multi-opcode general-purpose sequential processor over Fully Homomorphic Encryption (FHE) for Secure Multi-Party Computation (SMPC). VSP protects both the data and functions on which the data are evaluated from the adversary in a secure computation offloading situation like cloud computing. We proposed a complete processor architecture with a five-stage pipeline, which improves the performance of the VSP by providing more parallelism in circuit evaluation. In addition, we also designed a custom Instruction Set Architecture (ISA) to reduce the gate count of our processor, along with an entire set of toolchains to ensure that arbitrary C programs can be compiled into our custom ISA. In order to speed up instruction evaluation over VSP, CMUX Memory based ROM and RAM constructions over FHE are also proposed. Our experiments show that both the pipelined architecture and the CMUX Memory technique are effective in improving the performance of the proposed processor. We provide an open-source implementation of VSP which achieves a per-instruction latency of less than 1 second. We demonstrate that compared to the best existing processor over FHE, our implementation runs nearly 1,600$\times$ faster.