H S. Jacinto

A. Matthew Smith, H S. Jacinto

In this article we describe the characteristics of a large integrated linear optical device containing Mach-Zehnder interferometers and describe its potential use as a physically unclonable function. We propose that any tunable interferometric device of practical scale will be intrinsically unclonable and will possess an inherent randomness that can be useful for many practical applications. The device under test has the additional use-case as a general-purpose photonic manipulation tool, with various applications based on the experimental results of our prototype. Once our tunable interferometric device is set to work as a physically unclonable function, we find that there are approximately 6.85x10E35 challenge-response pairs, where each challenge can be quickly reconfigured by tuning the interferometer array for subsequent challenges.

Luka Daoud, Muhammad Kamran Latif, H S. Jacinto et al.

The scale invariant feature transform (SIFT) algorithm is considered a classical feature extraction algorithm within the field of computer vision. SIFT keypoint descriptor matching is a computationally intensive process due to the amount of data consumed. In this work, we designed a novel fully pipelined hardware accelerator architecture for SIFT keypoint descriptor matching. The accelerator core was implemented and tested on a field programmable gate array (FPGA). The proposed hardware architecture is able to properly handle the memory bandwidth necessary for a fully-pipelined implementation and hits the roofline performance model, achieving the potential maximum throughput. The fully pipelined matching architecture was designed based on the consine angle distance method. Our architecture was optimized for 16-bit fixed-point operations and implemented on hardware using a Xilinx Zynq-based FPGA development board. Our proposed architecture shows a noticeable reduction of area resources compared with its counterparts in literature, while maintaining high throughput by alleviating memory bandwidth restrictions. The results show a reduction in consumed device resources of up to 91 percent in LUTs and 79 percent of BRAMs. Our hardware implementation is 15.7 times faster than the comparable software approach.