Sk. Jahir Hossain

Shamim Ripon, Sk. Jahir Hossain, Keya Azad et al.

Formal verification of variant requirements has gained much interest in the software product line (SPL) community. Feature diagrams are widely used to model product line variants. However, there is a lack of precisely defined formal notation for representing and verifying such models. This paper presents an approach to modeling and verifying SPL variant feature diagrams using first-order logic. It provides a precise and rigorous formal interpretation of the feature diagrams. Logical expressions can be built by modeling variants and their dependencies by using propositional connectives. These expressions can then be validated by any suitable verification tool. A case study of a Computer Aided Dispatch (CAD) system variant feature model is presented to illustrate the verification process.

Shamim Ripon, Sk. Jahir Hossain, Touhid Bhuiyan

Modelling software product line (SPL) features plays a crucial role to a successful development of SPL. Feature diagram is one of the widely used notations to model SPL variants. However, there is a lack of precisely defined formal notations for representing and verifying such models. This paper presents an approach that we adopt to model SPL variants by using UML and subsequently verify them by using first-order logic. UML provides an overall modelling view of the system. First-order logic provides a precise and rigorous interpretation of the feature diagrams. We model variants and their dependencies by using propositional connectives and build logical expressions. These expressions are then validated by the Alloy verification tool. The analysis and verification process is illustrated by using Computer Aided Dispatch (CAD) system.