Jie Han

Jie Han, Peter Keevash

We consider the algorithmic decision problem that takes as input an $n$-vertex $k$-uniform hypergraph $H$ with minimum codegree at least $m-c$ and decides whether it has a matching of size $m$. We show that this decision problem is fixed parameter tractable with respect to $c$. Furthermore, our algorithm not only decides the problem, but actually either finds a matching of size $m$ or a certificate that no such matching exists. In particular, when $m=n/k$ and $c=O(\log n)$, this gives a polynomial-time algorithm, that given any $n$-vertex $k$-uniform hypergraph $H$ with minimum codegree at least $n/k-c$, finds either a perfect matching in $H$ or a certificate that no perfect matching exists.

Luyining Gan, Jie Han

Given $1\le \ell <k$ and $δ\ge0$, let $\textbf{PM}(k,\ell,δ)$ be the decision problem for the existence of perfect matchings in $n$-vertex $k$-uniform hypergraphs with minimum $\ell$-degree at least $δ\binom{n-\ell}{k-\ell}$. For $k\ge 3$, $\textbf{PM}(k,\ell,0)$ was one of the first NP-complete problems by Karp. Keevash, Knox and Mycroft conjectured that $\textbf{PM}(k, \ell, δ)$ is in P for every $δ> 1-(1-1/k)^{k-\ell}$ and verified the case $\ell=k-1$. In this paper we show that this problem can be reduced to the study of the minimum $\ell$-degree condition forcing the existence of fractional perfect matchings. Together with existing results on fractional perfect matchings, this solves the conjecture of Keevash, Knox and Mycroft for $\ell\ge 0.4k$. Moreover, we also supply an algorithm that outputs a perfect matching, provided that one exists.

Ruizhe Cai, Ao Ren, Olivia Chen et al.

The Adiabatic Quantum-Flux-Parametron (AQFP) superconducting technology has been recently developed, which achieves the highest energy efficiency among superconducting logic families, potentially huge gain compared with state-of-the-art CMOS. In 2016, the successful fabrication and testing of AQFP-based circuits with the scale of 83,000 JJs have demonstrated the scalability and potential of implementing large-scale systems using AQFP. As a result, it will be promising for AQFP in high-performance computing and deep space applications, with Deep Neural Network (DNN) inference acceleration as an important example. Besides ultra-high energy efficiency, AQFP exhibits two unique characteristics: the deep pipelining nature since each AQFP logic gate is connected with an AC clock signal, which increases the difficulty to avoid RAW hazards; the second is the unique opportunity of true random number generation (RNG) using a single AQFP buffer, far more efficient than RNG in CMOS. We point out that these two characteristics make AQFP especially compatible with the \emph{stochastic computing} (SC) technique, which uses a time-independent bit sequence for value representation, and is compatible with the deep pipelining nature. Further, the application of SC has been investigated in DNNs in prior work, and the suitability has been illustrated as SC is more compatible with approximate computations. This work is the first to develop an SC-based DNN acceleration framework using AQFP technology.

Xiaolong Ma, Yipeng Zhang, Geng Yuan et al.

With recent trend of wearable devices and Internet of Things (IoTs), it becomes attractive to develop hardware-based deep convolutional neural networks (DCNNs) for embedded applications, which require low power/energy consumptions and small hardware footprints. Recent works demonstrated that the Stochastic Computing (SC) technique can radically simplify the hardware implementation of arithmetic units and has the potential to satisfy the stringent power requirements in embedded devices. However, in these works, the memory design optimization is neglected for weight storage, which will inevitably result in large hardware cost. Moreover, if conventional volatile SRAM or DRAM cells are utilized for weight storage, the weights need to be re-initialized whenever the DCNN platform is re-started. In order to overcome these limitations, in this work we adopt an emerging non-volatile Domain-Wall Memory (DWM), which can achieve ultra-high density, to replace SRAM for weight storage in SC-based DCNNs. We propose DW-CNN, the first comprehensive design optimization framework of DWM-based weight storage method. We derive the optimal memory type, precision, and organization, as well as whether to store binary or stochastic numbers. We present effective resource sharing scheme for DWM-based weight storage in the convolutional and fully-connected layers of SC-based DCNNs to achieve a desirable balance among area, power (energy) consumption, and application-level accuracy.