Philippe Sauter

Axel Vanoni, Philippe Sauter, Paul Scheffler et al. · eth-zurich

Recent announcements have shown the viability of end-to-end open-source (OS) Linux-capable RISC-V systems on chip (SoCs). However, practical application and software development platforms require efficient non-volatile storage, which is not adequately served by common SPI-based interfaces due to their limited throughput. Secure Digital (SD) cards are the de facto standard storage medium for embedded Linux systems; efficient SD host controller (SDHC) integration is thus essential for open-source RISC-V platforms. We present an OS SD host controller interface (SDHCI) peripheral integrated into the end-to-end OS Cheshire RISC-V SoC platform. The controller and its software stack are designed with full awareness of CVA6's memory system and Linux driver behavior; during evaluation, we identify a significant performance bottleneck caused by the RISC-V memory model and CVA6's implementation of the fence instruction, which flushes the pipeline and data cache on memory-mapped register accesses when cache management operations (CMOs) are unavailable. By customizing the driver's register access paths and avoiding unnecessary fences, we substantially reduced this overhead. Our fully OS controller achieves up to 11.1 MB/s throughput, approaching the 12.5 MB/s limit of the SD interface and providing up to 6.5 times the throughput of SPI-based storage.

Michael Rogenmoser, Philippe Sauter, Chen Wu et al.

Single-event upset (SEU) fault tolerance for systems-on-chip (SoCs) in radiation-heavy environments is often addressed by architectural fault-tolerance approaches protecting individual SoC components (e.g., cores, memories) in isolation. However, the protection of voting logic and interconnections among components is also critical, as these become single points of failure in the design. We investigate combining multiple fault-tolerance approaches targeting individual SoC components, including interconnect and voting logic to ensure end-to-end SoC-level architectural SEU fault tolerance, while minimizing implementation area overheads. Enforcing an overlap between the protection methods ensures hardening of the whole design without gaps, while curtailing overheads. We demonstrate our approach on a RISC-V microcontroller SoC. SEU fault-tolerance is assessed with simulation-based fault injection. Overheads are assessed with full physical implementation. Tolerance to over 99.9% of faults in both RTL and implemented netlist is demonstrated. Furthermore, the design exhibits 22% lower implementation overhead compared to a single global fault-tolerance method, such as fine-grained triplication.

Philippe Sauter, Thomas Benz, Paul Scheffler et al.

Domain-Specific architectures with accelerators for machine learning and signal processing require efficient bulk data movement and high-bandwidth access to large datasets. Such capabilities are often absent from minimal open-source microcontrollers (MCUs). We present HyperCroc, an extension to the end-to-end open-source RISC-V Croc system-on-chip (SoC) integrating a silicon-proven HyperBus controller for off-chip DRAM and Flash memory access and a DMA engine, providing a practical MCU-class platform with streamlined plug-in support for domain-specific acceleration. HyperBus offers a low-pin-count PSDRAM interface at up to 400 MB/s, enabling bandwidth-scaled dataset access, while the DMA engine enables autonomous, high-throughput transfers without CPU intervention. HyperCroc preserves Croc's open-source synthesis and physical implementation flow targeting IHP's open 130 nm process design kit (PDK); the full chip can be implemented in under one hour on a consumer-grade workstation. We further report first silicon measurements from MLEM, the first Croc tapeout, confirming that the silicon is fully functional at 72 MHz @ 1.2 V and validating the end-to-end flow.