50.1LGApr 13
Physics-informed AI Accelerated Retention Analysis of Ferroelectric Vertical NAND: From Day-Scale TCAD to Second-Scale Surrogate ModelGyujun Jeong, Sungwon Cho, Minji Shon et al.
Ferroelectric field-effect transistors (FeFET)-based vertical NAND (Fe-VNAND) has emerged as a promising candidate to overcome z-scaling limitations with lower programming voltages. However, the data retention of 3D Fe-VNAND is hindered by the complex interaction between charge detrapping and ferroelectric depolarization. Developing optimized device designs requires exploring an extensive parameter space, but the high computational cost of conventional Technology Computer-Aided Design (TCAD) tools makes such wide-scale optimization impractical. To overcome these simulation barriers, we present a Physics-Informed Neural Operator (PINO)-based AI surrogate model designed for high-efficiency prediction of threshold voltage (Vth) shifts and retention behavior. By embedding fundamental physical principles into the learning architecture, our PINO framework achieves a speedup exceeding 10000x compared to TCAD while maintaining physical accuracy. This study demonstrates the model's effectiveness on a single FeFET configuration, serving as a pathway toward modeling the retention loss mechanisms.
40.3ARMar 12
System-Technology Co-Optimization of Bitline Routing and Bonding Pathways in Monolithic 3D DRAM ArchitecturesKiseok Lee, Sungwon Cho, Seongkwang Lim et al.
3D DRAM has emerged as a promising approach for continued density scaling, but its viability is limited by routing and hybrid bonding constraints to periphery, which may degrade sensing margin, latency, and array efficiency. With device characteristics and array parasitics extracted from TCAD, SPICE simulations are performed with peri logic in a CMOS-Bonded-Array (CBA). The analysis shows that the bitline strap architecture with amorphous oxide semiconductor (AOS) selectors is essential to manage routing congestion and parasitics. The optimized design achieves a bit density of 2.6 Gb/mm^2 (137 layers with Si access transistors or 87 layers with AOS), representing ~6x density scaling over D1b 2D DRAM. The design further demonstrates a nominal row cycle time (tRC) of 10.5 ns, compared to 21.3 ns in D1b, and a 60% reduction in read/write energy.