Jürgen Teich

Abrarul Karim, Joachim Falk, Jürgen Teich

The introduction of dynamic power management strategies such as clock gating and power gating in dataflow networks has been shown to provide significant energy savings when applied during idle times. However, these strategies can also degrade throughput due to shutdown and wake-up delays. Such throughput degradations might be particularly detrimental to signal processing systems that require a guaranteed throughput. As a solution, this paper first contributes a linear-program formulation for finding a periodic maximal-throughput schedule of a given so-called self-powering dataflow network where actors, realized in hardware, are allowed to go to sleep whenever not being enabled to fire. Depending on which actors are allowed to power down, tradeoffs between throughput and energy savings can be obtained. As a second contribution, we propose a mixed-integer-linear-program formulation to determine a periodic schedule that satisfies a given throughput while minimizing the overall energy per period by identifying a respective set of actors that is allowed to power down in phases of idleness and which rather not. Finally, as a third contribution, we propose a multi-objective design-space exploration strategy called "Hop and Skip" to efficiently explore the Pareto front of energy and throughput solutions. Experimental evaluations on a set of existing benchmarks and randomly generated graphs witness significant exploration time reductions over a brute-force sweep. Finally, a real-world case study is elaborated, and we report on achievable energy savings and throughputs of the related dataflow network where (a) all actors are always-active, (b) all actors are self-powered, and (c) all optimal energy and throughput tradeoff points as found by the proposed design-space exploration strategy.

Dominik Walter, Frank Hannig, Jürgen Teich

Multidimensional loop kernels often suffer from control overhead that can dominate execution time on parallel loop accelerators. Tightly Coupled Processor Arrays (TCPAs) offload loop control to a global controller (GC), but existing approaches still require hundreds of control signals. We propose a method to derive and aggressively reduce these control conditions from a polyhedral representation of the iteration space, achieving reductions of 15x to 45x in control signals across several benchmarks. We introduce a lightweight GC architecture that evaluates conditions as unions of polyhedra using bounded evaluation units, requiring hardware comparable to a single processing element. Control signals are distributed throughout the array with a minimal number of delay elements resulting in zero-overhead loop control. Our evaluation on PolyBench kernels shows that the entire control flow requires < 10 % of the total array resources.

Avinash Mahesh Nirmala, Dominik Walter, Frank Hannig et al.

This work presents a symbolic approach for estimating the energy consumption for nested loop programs when mapped and scheduled on parallel processor array accelerator architectures. Instead of simulation-based evaluation, we derive a methodology for symbolic energy analysis that captures the impact of mapping and scheduling decisions of loop nests on processor arrays. We compare our approach against simulation-based results for selected benchmarks and varying sizes of the iteration spaces. Whereas the latter are not scalable, our symbolic analysis is shown to be independent of the problem size. The presented evaluation methodology can be beneficially used during the design space exploration of mapping and scheduling decisions, for studying the influence of array size variations, and for comparisons with other loop nest accelerator architectures.