Oskar von Seeler

Oskar von Seeler, Christian Tetzlaff, Andrew Lehr

In biological circuits, sequential neural activity evolves along dynamic, low-dimensional manifolds to enable flexible behavior. Spiking network models link aspects of this sequential activity to features of manifold geometry through specific circuit mechanisms, making dynamic neural manifolds parameterizable, and thereby offering an explainable framework for neural computation. Extending this framework to neuromorphic engineering, we present an implementation on the SpiNNaker 2 chip for real-time, closed-loop control. By allowing sensory inputs to modulate heterogeneous inhibition, gain, and transient currents, our architecture drives rapid subspace rotations to switch between behaviors, as well as fine-grained trajectory control within them. We validate this via a robotic simulation where an agent uses sensory feedback to dynamically reconfigure its manifold geometry to navigate through a maze. Our results establish dynamic manifolds as a feasible approach for explainable neuromorphic architectures and a substrate for investigating biological neural dynamics.

Oskar von Seeler, Elena C. Offenberg, Carlo Michaelis et al.

Efficient computation of shortest paths in weighted graphs is a fundamental problem with many applications. Neuromorphic hardware platforms promise massively parallel, efficient computation, changing parallelism tradeoffs. In this work, we introduce NEURO-MAPP (Neuromorphic-based Min-Add Parallel Propagation), a distributed shortest path algorithm designed to use the local computation and network communication available in neuromorphic systems. We provide an optimized implementation of the algorithm on the SpiNNaker 2 platform and evaluate its performance on a selection of synthetic and real-world graphs. These results are compared to Dijkstra's algorithm on a modern CPU. We find that the NEURO-MAPP implementation scales favorably in terms of runtime for many graph types while consuming less energy per shortest-path query than the CPU implementation in almost all cases. These findings highlight the potential of neuromorphic hardware featuring sparse, spike-based communication as a scalable and energy-efficient platform for computation in graph search and related tasks.