Muhammad Usman

Muhammad Usman, Malik Zohaib Nisar, Florian Aschauer et al.

We present MINT, a dynamic-precision CNN inference accelerator based on left-to-right (LR) arithmetic. LR arithmetic computes in most-significant-digit-first manner and exposes useful partial results early so that the computation can be terminated once the desired precision is achieved. At the core, there is a MSDF serial-parallel inner-product unit, which uses redundant signed-digit representation to compute each convolution window. A budget-constrained greedy search profiles all convolution layers from INT2 to INT7 and selects the lowest precision per layer while constraining total accuracy loss to within 2\% of the INT8 baseline for VGG-16 and ResNet-18 networks. The design is synthesized on a Xilinx Zynq-7020 at \SI{200}{\mega\hertz}, and uses 5.64 average bits for VGG-16 and 6.04 for ResNet-18, while achieving 19.86 GOPS and 29.51 GOPS/W on VGG-16, and 18.86 GOPS and 26.40 GOPS/W on ResNet-18. This corresponds to 32.6\% and 26.0\% higher throughput and 82.10\% and 62.90\% higher energy efficiency than INT8 with only 1.81\% and 1.96\% drops relative to the INT8 baseline. Compared with representative prior FPGA CNN accelerators considered in this study, MINT delivers the highest energy efficiency among the listed VGG-16 and ResNet-18 designs on Zynq-7020 platform.

Muhammad Usman, Shujaat Khan, Dorit Merhof

Adder trees are the computational backbone of delay-and-sum (DAS) ultrasound beamforming, where their implementation directly determines the energy, throughput, and area of a real-time imaging pipeline. Conventional parallel adder trees perform full-precision combinational reduction on every sample, leading to wide critical paths, high LUT consumption, and timing failures on small FPGA devices. This paper presents an alternative adder tree architecture based on \emph{left-to-right (LR)} or \emph{most significant digit first (MSDF) arithmetic}. We implement the proposed and conventional adder trees on a Xilinx Zynq XC7Z010 FPGA and evaluate them for DAS beamforming of a 64-channel ultrasound dataset. The proposed design uses 2.5$\times$ fewer LUTs than the smallest conventional tree, successfully meets the timing constraint, and consumes 23\% less dynamic power than the most efficient conventional baseline. A key advantage of the proposed MSDF adder tree is that it can generate high-quality beamformed images without waiting for full-precision completion. This naturally enables dynamic precision at runtime with negligible control overhead, since precision selection is achieved simply by stopping the computation clock after the desired number of cycles. Such quality--energy scalability is fundamentally unavailable in conventional fixed-cycle adder trees. Iso-area replication enables up to 15 parallel instances on the XC7Z010, achieving 67 FPS, which is 80\% higher throughput than the best conventional design.