Christian Tetzlaff

Oskar von Seeler, Christian Tetzlaff, Andrew Lehr

In biological circuits, sequential neural activity evolves along dynamic, low-dimensional manifolds to enable flexible behavior. Spiking network models link aspects of this sequential activity to features of manifold geometry through specific circuit mechanisms, making dynamic neural manifolds parameterizable, and thereby offering an explainable framework for neural computation. Extending this framework to neuromorphic engineering, we present an implementation on the SpiNNaker 2 chip for real-time, closed-loop control. By allowing sensory inputs to modulate heterogeneous inhibition, gain, and transient currents, our architecture drives rapid subspace rotations to switch between behaviors, as well as fine-grained trajectory control within them. We validate this via a robotic simulation where an agent uses sensory feedback to dynamically reconfigure its manifold geometry to navigate through a maze. Our results establish dynamic manifolds as a feasible approach for explainable neuromorphic architectures and a substrate for investigating biological neural dynamics.

Carlo Michaelis, Andrew B. Lehr, Winfried Oed et al.

Developing intelligent neuromorphic solutions remains a challenging endeavour. It requires a solid conceptual understanding of the hardware's fundamental building blocks. Beyond this, accessible and user-friendly prototyping is crucial to speed up the design pipeline. We developed an open source Loihi emulator based on the neural network simulator Brian that can easily be incorporated into existing simulation workflows. We demonstrate errorless Loihi emulation in software for a single neuron and for a recurrently connected spiking neural network. On-chip learning is also reviewed and implemented, with reasonable discrepancy due to stochastic rounding. This work provides a coherent presentation of Loihi's computational unit and introduces a new, easy-to-use Loihi prototyping package with the aim to help streamline conceptualisation and deployment of new algorithms.

Oskar von Seeler, Elena C. Offenberg, Carlo Michaelis et al.

Efficient computation of shortest paths in weighted graphs is a fundamental problem with many applications. Neuromorphic hardware platforms promise massively parallel, efficient computation, changing parallelism tradeoffs. In this work, we introduce NEURO-MAPP (Neuromorphic-based Min-Add Parallel Propagation), a distributed shortest path algorithm designed to use the local computation and network communication available in neuromorphic systems. We provide an optimized implementation of the algorithm on the SpiNNaker 2 platform and evaluate its performance on a selection of synthetic and real-world graphs. These results are compared to Dijkstra's algorithm on a modern CPU. We find that the NEURO-MAPP implementation scales favorably in terms of runtime for many graph types while consuming less energy per shortest-path query than the CPU implementation in almost all cases. These findings highlight the potential of neuromorphic hardware featuring sparse, spike-based communication as a scalable and energy-efficient platform for computation in graph search and related tasks.

Sebastian Herzog, Christian Tetzlaff, Florentin Wörgötter

The structure of the majority of modern deep neural networks is characterized by uni- directional feed-forward connectivity across a very large number of layers. By contrast, the architecture of the cortex of vertebrates contains fewer hierarchical levels but many recurrent and feedback connections. Here we show that a small, few-layer artificial neural network that employs feedback will reach top level performance on a standard benchmark task, otherwise only obtained by large feed-forward structures. To achieve this we use feed-forward transfer entropy between neurons to structure feedback connectivity. Transfer entropy can here intuitively be understood as a measure for the relevance of certain pathways in the network, which are then amplified by feedback. Feedback may therefore be key for high network performance in small brain-like architectures.