Prianka Sengupta

Cristhian Roman-Vicharra, Prianka Sengupta, Runzhi Wang et al.

In heterogeneous integration, different dies may employ distinct technologies, making floorplanning across multiple dies inherently coupled with technology assignment. By assuming a fixed technology, almost all prior floorplanning studies were developed without addressing the challenge of technology assignment. This work presents the first systematic study of multi-die floorplanning that treats technology choice as a variable. To address the challenge of variable block areas, we incorporate a recent machine learning technique for rapid PPA estimation. Our methods jointly optimize area, wirelength, performance, power, and cost, thereby highlighting the importance of technology assignment. Experimental evaluations, validated with a commercial tool for both 2.5D and 3D ICs, demonstrate that our systematic optimizations significantly outperform a greedy approach.

Runzhi Wang, Prianka Sengupta, Cristhian Roman-Vicharra et al.

In chip design planning, obtaining reliable performance and power forecasts for various design options is of critical importance. Traditionally, this involves using system-level models, which often lack accuracy, or trial synthesis, which is both labor-intensive and time-consuming. We introduce a new methodology, called Lorecast, which accepts English prompts as input to rapidly generate layout-aware performance and power estimates. This approach bypasses the need for HDL code development and synthesis, making it both fast and user-friendly. Experimental results demonstrate that Lorecast achieves accuracy within a few percent of error compared to post-layout analysis, while significantly reducing turnaround time.