Gwan Choi

Pravir Singh Gupta, Xin Yuan, Gwan Seong Choi

We investigate the power and performance improvement in image acquisition devices by the use of CAS (Compressed Acquisition Scheme) and DNN (Deep Neural Networks). Towards this end, we propose a novel image acquisition scheme HCAS (Hardware based Compressed Acquisition Scheme) using hardware-based binning (downsampling), bit truncation and JPEG compression and develop a deep learning based reconstruction network for images acquired using the same. HCAS is motivated by the fact that in-situ compression of raw data using binning and bit truncation results in reduction in data traffic and power in the entire downstream image processing pipeline and additional compression of processed data using JPEG will help in storage/transmission of images. The combination of in-situ compression with JPEG leads to high compression ratios, significant power savings with further advantages of image acquisition simplification. Bearing these concerns in mind, we propose DRCAS (Deep Restoration network for hardware based Compressed Acquisition Scheme), which to our best knowledge, is the first work proposed in the literature for restoration of images acquired using acquisition scheme like HCAS. When compared with the CAS methods (bicubic downsampling) used in super resolution tasks in literature, HCAS proposed in this paper performs superior in terms of both compression ratio and being hardware friendly. The restoration network DRCAS also perform superior than state-of-the-art super resolution networks while being much smaller. Thus HCAS and DRCAS technique will enable us to design much simpler and power efficient image acquisition pipelines.

Ehsan Rohani, Gwan Choi, Mi Lu

In this paper we introduce the algorithm and the fixed point hardware to calculate the normalized singular value decomposition of a non-symmetric matrices using Givens fast (approximate) rotations. This algorithm only uses the basic combinational logic modules such as adders, multiplexers, encoders, Barrel shifters (B-shifters), and comparators and does not use any lookup table. This method in fact combines the iterative properties of singular value decomposition method and CORDIC method in one single iteration. The introduced architecture is a systolic architecture that uses two different types of processors, diagonal and non-diagonal processors. The diagonal processor calculates, transmits and applies the horizontal and vertical rotations, while the non-diagonal processor uses a fully combinational architecture to receive, and apply the rotations. The diagonal processor uses priority encoders, Barrel shifters, and comparators to calculate the rotation angles. Both processors use a series of adders to apply the rotation angles. The design presented in this work provides $2.83\sim649$ times better energy per matrix performance compared to the state of the art designs. This performance achieved without the employment of pipelining; a better performance advantage is expected to be achieved employing pipelining.