John Gustafson

Rishi Thotli, Aditya Anirudh Jonnalagadda, Rishabh Hulsurkar et al.

In modern computing units, division operations are generally slower than other arithmetic operations and require more resources, such as area and power, than multiplication. To reduce the delay, fast division algorithms use an initial approximation of the reciprocal of the divisor and iteratively approach the correct value, followed by multiplication with the dividend. The hardware architecture and choice of algorithm can significantly alter the overall performance of the division unit. This paper proposes a reduced-accuracy division method for the posit number system, which is an alternative to the traditional floating-point system. The proposed design uses a Look-Up Table (LUT) and a single subtraction operation to perform approximate divisor reciprocation by leveragingthemathematicalsymmetriesofthepositnumbersystem.The paper also presents a hardware architecture that combines multiplication and division units. The reciprocal calculation has been incorporated into the posit Decoder, a common unit required to perform any hardware operation with posits. Compared to existing hardware implementations of division, the proposed method requires significantly fewer operations at the cost of perfect rounding for division. The proposed architecture was simulated using the Cadence RTL v7.1 E2 compiler at the TSMC 90 nm process node and achieves a Power Delay Product (PDP) reduction of 78.8% compared to an existing design that performs exact division, while only 46.33% of the area is required. The experimental results also demonstrate the effectiveness of the proposed system in improving the efficiency of multiplication in posit-based systems.

Akshat Ramachandran, Zishen Wan, Geonhwa Jeong et al.

Traditional Deep Neural Network (DNN) quantization methods using integer, fixed-point, or floating-point data types struggle to capture diverse DNN parameter distributions at low precision, and often require large silicon overhead and intensive quantization-aware training. In this study, we introduce Logarithmic Posits (LP), an adaptive, hardware-friendly data type inspired by posits that dynamically adapts to DNN weight/activation distributions by parameterizing LP bit fields. We also develop a novel genetic-algorithm based framework, LP Quantization (LPQ), to find optimal layer-wise LP parameters while reducing representational divergence between quantized and full-precision models through a novel global-local contrastive objective. Additionally, we design a unified mixed-precision LP accelerator (LPA) architecture comprising of processing elements (PEs) incorporating LP in the computational datapath. Our algorithm-hardware co-design demonstrates on average <1% drop in top-1 accuracy across various CNN and ViT models. It also achieves ~ 2x improvements in performance per unit area and 2.2x gains in energy efficiency compared to state-of-the-art quantization accelerators using different data types.