Wajid Ali

Abdullah Azhar, Uneeb Kamal, Wajid Ali et al.

This paper presents the design and physical implementation of UET-RVMCU, a lightweight RISC-V microcontroller derived from the UETRV-PCore. Aimed at creating an accessible and flexible open-source RISC-V-based microcontroller, UET-RVMCU simplifies the application-class UETRV-PCore by reducing pipeline stages, removing MMU functionality, and integrating GPIO peripherals. The final GDSII layout was generated using an open-source RTL-to-GDS flow (OpenLane). This project demonstrates the feasibility of transforming an application-class SoC into a feature-rich microcontroller suitable for embedded systems, emphasizing low area, design simplicity, and open-source development.

Wajid Ali, Ayaz Akram

This paper presents our approach to accelerate computer architecture simulation by leveraging machine learning techniques. Traditional computer architecture simulations are time-consuming, making it challenging to explore different design choices efficiently. Our proposed model utilizes a combination of application features and micro-architectural features to predict the performance of an application. These features are derived from simulations of a small portion of the application. We demonstrate the effectiveness of our approach by building and evaluating a machine learning model that offers significant speedup in architectural exploration. This model demonstrates the ability to predict IPC values for the testing data with a root mean square error of less than 0.1.