Eashan Wadhwa

Eashan Wadhwa, Georgios Floros, Shanker Shreejith

Pre-implementation behavioural simulation routinely validates functional correctness, yet it also produces rich switching-activity traces that are typically discarded by FPGA computer-aided design (CAD) flows. Prior simulation-guided and power-aware FPGA optimisations demonstrate the promise of exploiting this metadata, but many rely on fixed thresholds, narrow decision heuristics, or limited design awareness, often incurring substantial area overhead. This paper presents Context-aware Simopt-Power, a simulator-guided optimisation framework that combines activity metadata with lightweight structural features (sequential proximity, logic-depth proxies, and fan-out estimates) to more precisely target high-impact regions of the netlist. We additionally remove empirically tuned constants, replacing them with architecture-aware parameters such as LUT size and mapping constraints, and evaluate trade-offs using power, delay, and a more useful metrics, area-delay product (AD) and power-delay product (PD). Implemented in an open-source Yosys/ABC flow and evaluated on the complex Koios deep-learning accelerator benchmarks, Context-aware Simopt-Power achieves an average 6.8% dynamic-power reduction while limiting LUT overhead to 11.2%, thus enabling a holistic design optimisation.

Shashwat Khandelwal, Eashan Wadhwa, Shreejith Shanker

Rising complexity of in-vehicle electronics is enabling new capabilities like autonomous driving and active safety. However, rising automation also increases risk of security threats which is compounded by lack of in-built security measures in legacy networks like CAN, allowing attackers to observe, tamper and modify information shared over such broadcast networks. Various intrusion detection approaches have been proposed to detect and tackle such threats, with machine learning models proving highly effective. However, deploying machine learning models will require high processing power through high-end processors or GPUs to perform them close to line rate. In this paper, we propose a hybrid FPGA-based ECU approach that can transparently integrate IDS functionality through a dedicated off-the-shelf hardware accelerator that implements a deep-CNN intrusion detection model. Our results show that the proposed approach provides an average accuracy of over 99% across multiple attack datasets with 0.64% false detection rates while consuming 94% less energy and achieving 51.8% reduction in per-message processing latency when compared to IDS implementations on GPUs.