Saraju P. Mohanty

Venkata Prasanth Yanambaka, Uma Choppali, Saraju P. Mohanty

The Internet of Things (IoT) was introduced almost two decades ago. In the past two decades, technology has seen huge advancements. Many devices have become powerful and have less power consumption. Many IoT architectures and environments were introduced to help make life easier, especially in wearable devices. The market for these wearable devices has constantly increased over the years and is expected to reach its maximum in the next couple of years. They also pose a threat to users' privacy and security because they constantly store and transmit personal information such as location, heart rate, and other sensitive data. Therefore, addressing the security vulnerabilities is a crucial aspect of this research. This paper presents a hardware-assisted, energy-efficient, low-overhead security solution for wearable devices. Specifically, two Physical Unclonable Function (PUF) architectures: Arbiter PUF and Hybrid Oscillator Arbiter (HOA) PUF are analyzed for integration in IoT systems. The result shows that Arbiter PUF consumes 25 $μ$W, whereas HOA PUF consumes only 2.7 $μ$W to generate keys for cryptographic purposes. These architectures introduce minimal power overhead while providing robust security, making them well suited for resource-constrained IoT ecosystems.

Jayakrishna Amathi, Venkata Prasanth Yanambaka, Saraju P. Mohanty et al.

Despite the success of deep neural networks in vision, medical diagnosis, and IoT scenarios, their deployment on resource-limited platforms poses serious challenges due to their high storage requirements, computational complexity, and large footprint. In particular, fully connected layers require a large number of weights, making it difficult for edge devices to accommodate them. To overcome these challenges associated with limited platforms, this paper proposes the Two-Valued Symmetric Circulant Matrix (TVSCM), a very sparse architecture that employs just two weights per layer to keep it circulant and symmetric. The extreme form of structured sparse architecture provides negligible storage costs compared to traditional full-weight storage. Instead of hardware and additional stages of other traditional sparse learning techniques, such as low-rank approximation and pruning approaches, this architecture provides an extreme form of sparsity, achieving very minimal storage requirements. The simulation study demonstrates more than 80$\times$ reduction in model parameters, reducing parameters from 623,290 to 7,852 on MNIST and from 24,709 to 942 on the MIT-BIH arrhythmia dataset, while maintaining comparable accuracy from 97.6% to 93.5% on MNIST and from 97.6% to 93.1% on MIT-BIH. Due to its minimal architectural requirements and very low power consumption, this architecture would be ideal for edge computing platforms, tiny-ML platforms, IoMT systems, and battery-powered systems.