S. Krishnakumar

Sriharini Krishnakumar, Inna Partin-Vaisband

Distributed vertical power delivery has emerged as a promising approach to meet aggressive current-density, efficiency, and transient response requirements in high-performance computing systems. Tight integration of voltage regulators within stacked substrates, however, increases the vulnerability of the power delivery system to short-circuit and open-circuit faults arising from elevated thermal and mechanical stresses. Such faults can propagate through the shared power delivery network, leading to rapid degradation of system-wide efficiency at worst-case rates of up to 0.5% per microsecond. Advanced fault-tolerant power management strategies are therefore required to ensure efficient power delivery. A real-time fault-detection and isolation methodology are proposed in this paper for vertical power delivery systems. The methodology is developed based on an analytical inductor-current models that rely solely on signals available within the converter control circuitry, thereby eliminating additional sensing overhead. The proposed framework is designed and simulated in SPICE environment, demonstrating sub-microsecond fault detection and effective dual-fuse isolation, maintaining uninterrupted power delivery with a system-wide efficiency degradation of less than 2%.

Sriharini Krishnakumar, Inna Partin-Vaisband

Distributed vertical power delivery (DVPD) architectures employ multiple parallel voltage regulators (VRs) to meet the high-power and high current density demands of modern high performance computing (HPC) systems. While full parallel activation maximizes efficiency near peak load, medium to light load operation leads to efficiency degradation when all VRs remain active due to persistent switching and gate drive losses. This work proposes a load aware power system activation framework targeted at the medium to light load regime, in which the number of active VRs scales proportionally with instantaneous load power. A spatially informed selection strategy determines which VRs are activated from the available pool, aligning regulator placement with localized power demand. This locality aware activation minimizes lateral redistribution currents within the power plane and reduces conduction losses and voltage drops. Simulation results on a representative DVPD system demonstrate 2x to 3x switching loss reduction relative to conventional full-parallel light load operation, while sustaining an approximately 87% efficiency plateau across the 5% to 30% load range. Output ripple constraints are preserved, with inductor current ripple maintained within 6% and output voltage ripple within 2%, ensuring regulation integrity while improving overall conversion efficiency.

Sriharini Krishnakumar, Yaroslav Popryho, Mingeun Choi et al.

Power delivery -- including high-to-low voltage conversion, complex power distribution across heterogeneously integrated chiplets, and efficient interconnect allocation -- remains a critical bottleneck in high-performance computing (HPC) systems. Existing vertical power delivery (VPD) solutions are estimated to achieve less than 70\% system-wide end-to-end power delivery efficiency, defined from platform input power to delivered on-chip load power, with substantial energy lost as heat before reaching on-chip point-of-loads (POLs). In the absence of systematic design methodologies, evaluating power quality, exploring architectural alternatives, and optimizing performance rely on computationally prohibitive simulations, resulting in suboptimal designs. This paper introduces an end-to-end scalable power delivery framework for HPC systems, including distributed VPD (DVPD) architecture, DVPD design optimization methodology, and analytical models. The framework leverages substrate-embedded GaN power switches together with arrays of unit inductors and capacitors tailored for HPC applications. Multi-stage power conversion schemes (48V-to-1V, 48V-to-24V-to-1V, and 48V-to-12V-to-1V) are explored, with system-wide voltage drops and power losses evaluated under steady-state conditions. Design specifications for passive and active devices are formulated to meet next-generation efficiency targets. For the 48V-to-1V case, the proposed DVPD approach achieves 84\% system-wide efficiency while occupying 54\% of the area beneath the load system, with efficiency increasing to 87.6\% at 75\% area utilization across a 1--50~kW load range. Furthermore, steady-state voltage drops peak at 2.7\% and transient drops at 9\% (without decoupling capacitors), demonstrating the viability of DVPD for future wafer-scale HPC platforms.