Runhao Liu

Fei Ding, Yongkang Zhang, Runhao Liu et al.

Reasoning language models do not distinguish tokens used for computation from tokens that constitute persistent state: once generated, all hidden thoughts remain in context and influence future predictions. As a result, downstream reasoning may depend on failed attempts, dead ends, and private scratch work that should not be safely relied on later. We recast this phenomenon as a new training objective, state commitment learning: training models to explicitly distinguish information that should be committed as persistent state from temporary computation that can be discarded. We define a counterfactual criterion, persistent-state sufficiency, which makes it trainable and measurable whether an answer remains usable after hidden thoughts are erased. We then propose Counterfactual Erasure RL (CERL), which evaluates, under the same prefix, both a path that keeps hidden thoughts and a path that erases them, and gives reward only when the erasure path remains correct. We also introduce the Erasure Dependence Protocol and show across mathematics, long-chain logic, scientific QA, and multi-turn tool-use evaluation that CERL substantially reduces answer dependence on hidden thoughts without sacrificing accuracy, consistently outperforming correctness-only RL and long-answer SFT baselines.

Runhao Liu, Peng Zheng

Neural Processing Units (NPUs) are increasingly deployed for high-throughput, memory-constrained inference, yet their hierarchical on-chip memories and heterogeneous compute and data-movement engines tightly couple execution order, memory placement, and pipeline overlap. Existing compiler flows often optimize these dimensions separately, causing excessive on-chip residency, unnecessary off-chip traffic, and underutilized pipelines.We present DAN-Scheduler, a deterministic offline scheduling and compiler optimization framework for intra-core NPU execution. It co-optimizes these decisions in three stages. Memory-Pressure-Aware Topological Scheduling (MPAS) reorders operators to shorten tensor lifetimes and reduce peak on-chip memory usage. Deterministic Linear Repackaging (DLR) builds conflict-free memory layouts and applies a tier-aware, cost-aware spill heuristic to reduce fragmentation and off-chip traffic under limited capacity. Critical Path Enhancement (CPE) improves compute-DMA overlap while preserving the memory behavior established by the first two stages. We evaluate DAN-Scheduler on six trace-derived operator-level DAGs collected from a real Davinci NPU and replayed on a generalized NPU execution model. Against four strong external baselines, DAN-Scheduler achieves the best or tied-best result on all 24 workload-metric cells, reducing peak memory, extra DDR traffic, spill count, and makespan by 18.3%, 20.4%, 14.2%, and 16.3% on average over the best external competitor. Relative to the original schedule, it reduces the same metrics by 38.3%, 62.0%, 64.9%, and 57.5%. These results show that deterministic stage-wise co-optimization is effective for memory-constrained NPU execution. Code and data are available at https://anonymous.4open.science/r/MICRO2026-5C74