Gang Li

Minnan Pei, Gang Li, Zeyu Zhu et al.

3D Gaussian Splatting (3DGS) has emerged as a leading technique for real-time novel view synthesis, yet existing 3DGS accelerators suffer from poor architectural scalability: increasing the number of PEs leads to marginal performance improvement during rendering. We identify that the root cause is the tightly coupled ``checking-while-blending'' dataflow, which exacerbates PE underutilization caused by spatial redundancy from irregular Gaussian coverage and temporal redundancy from asynchronous pixel-wise termination under parallel execution. To address this issue, we propose DeGS, a scalable architecture for efficient 3DGS inference. To systematically eliminate the redundancies inherent in rendering, DeGS exploits a decoupled dataflow, restructuring the coupled $α$-checking, transmittance checking, and $α$-blending of the standard rendering process into consecutive workload parsing, reorganization, and blending stages. This allows the fragmented, length-variable, and temporal-dependent workloads to be reorganized into compact, conflict-free, and dense workloads prior to blending, thereby significantly improving PE utilization during parallel blending. Implemented in 28 nm technology, DeGS achieves 2.36$\times$--7.25$\times$ throughput, 1.82$\times$--6.02$\times$ end-to-end speedup, and 1.59$\times$--4.42$\times$ energy efficiency over state-of-the-art 3DGS accelerators (GSCore, GBU, GCC) across diverse scenes and resolutions (720p to 8K). Moreover, scaling from 16 to 1024 PEs, DeGS maintains over 80\% PE utilization at high resolutions, significantly outperforming existing accelerators.

Runhao Liu, Peng Zheng

Neural Processing Units (NPUs) are increasingly deployed for high-throughput, memory-constrained inference, yet their hierarchical on-chip memories and heterogeneous compute and data-movement engines tightly couple execution order, memory placement, and pipeline overlap. Existing compiler flows often optimize these dimensions separately, causing excessive on-chip residency, unnecessary off-chip traffic, and underutilized pipelines.We present DAN-Scheduler, a deterministic offline scheduling and compiler optimization framework for intra-core NPU execution. It co-optimizes these decisions in three stages. Memory-Pressure-Aware Topological Scheduling (MPAS) reorders operators to shorten tensor lifetimes and reduce peak on-chip memory usage. Deterministic Linear Repackaging (DLR) builds conflict-free memory layouts and applies a tier-aware, cost-aware spill heuristic to reduce fragmentation and off-chip traffic under limited capacity. Critical Path Enhancement (CPE) improves compute-DMA overlap while preserving the memory behavior established by the first two stages. We evaluate DAN-Scheduler on six trace-derived operator-level DAGs collected from a real Davinci NPU and replayed on a generalized NPU execution model. Against four strong external baselines, DAN-Scheduler achieves the best or tied-best result on all 24 workload-metric cells, reducing peak memory, extra DDR traffic, spill count, and makespan by 18.3%, 20.4%, 14.2%, and 16.3% on average over the best external competitor. Relative to the original schedule, it reduces the same metrics by 38.3%, 62.0%, 64.9%, and 57.5%. These results show that deterministic stage-wise co-optimization is effective for memory-constrained NPU execution. Code and data are available at https://anonymous.4open.science/r/MICRO2026-5C74