Memory Based Machine Intelligence Techniques in VLSI hardware
This addresses the practical problem of hardware implementation for AI researchers and engineers, but appears incremental as it reviews existing approaches without introducing new methods.
The paper tackles the challenge of implementing machine intelligence techniques like deep architectures and memory networks in VLSI hardware, aiming to provide scalable solutions for tasks such as sparse coding and contextual processing, but does not report specific results or numbers.
We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high level intelligence problems such as sparse coding and contextual processing.