CROct 17, 2012
Several AES Variants under VHDL language In FPGA
arXiv:1210.4962v14 citations
Originality Synthesis-oriented
AI Analysis
This work addresses hardware optimization for AES encryption in embedded systems, but it is incremental as it applies existing methods to new FPGA platforms.
The paper tackled the implementation of AES encryption variants in FPGA hardware, resulting in four architectures tested on Altera Cyclone III and STRATIX devices with performance metrics like speed and area usage.
This paper provides four different architectures for encrypting and decrypting 128 bit information via the AES. The encryption algorithm includes the Key Expansion module which generates Key for all iterations on the fly, Double AEStwo-key triple AES, AESX and AES-EXE. These architectures are implemented and studied in Altera Cyclone III and STRATIX Family devices.