Sequence Diagram Test Case Specification and Virtual Integration Analysis using Timed-Arc Petri Nets
This work addresses the need for early error identification in component-based designs, particularly in safety-critical domains like avionics, though it appears incremental as it builds on existing UML and Petri net methods.
The paper tackles the problem of specifying test cases with timing constraints for component-based systems by formally defining Test Case Sequence Diagrams (TCSD) and transforming them into timed-arc Petri nets for virtual integration analysis, demonstrating applicability on an avionic use case from the ARP4761 standard.
In this paper, we formally define Test Case Sequence Diagrams (TCSD) as an easy-to-use means to specify test cases for components including timing constraints. These test cases are modeled using the UML2 syntax and can be specified by standard UML-modeling-tools. In a component-based design an early identification of errors can be achieved by a virtual integration of components before the actual system is build. We define such a procedure which integrates the individual test cases of the components according to the interconnections of a given architecture and checks if all specified communication sequences are consistent. Therefore, we formally define the transformation of TCSD into timed-arc Petri nets and a process for the combination of these nets. The applicability of our approach is demonstrated on an avionic use case from the ARP4761 standard.