Hardware Implementation of Algorithm for Cryptanalysis
This work addresses the need for faster cryptanalysis in cryptography, but it is incremental as it applies existing methods to hardware implementation without major breakthroughs.
The paper tackled the problem of speeding up cryptanalysis of block ciphers by implementing an exhaustive key search for the Data Encryption Standard (DES) on FPGA hardware, comparing rolled and unrolled architectures and selecting the rolled one based on experimental results to achieve faster performance.
Cryptanalysis of block ciphers involves massive computations which are independent of each other and can be instantiated simultaneously so that the solution space is explored at a faster rate. With the advent of low cost Field Programmable Gate Arrays, building special purpose hardware for computationally intensive applications has now become possible. For this the Data Encryption Standard is used as a proof of concept. This paper presents the design for Hardware implementation of DES cryptanalysis on FPGA using exhaustive key search. Two architectures viz. Rolled and Unrolled DES architecture are compared and based on experimental result the Rolled architecture is implemented on FPGA. The aim of this work is to make cryptanalysis faster and better.