Hardware Implementation of the GPS authentication
This work addresses hardware resource optimization for GPS authentication in embedded systems like sensors, but it is incremental as it builds on existing protocols and multipliers.
The paper tackles the trade-off between area and throughput in implementing the GPS authentication protocol by exploiting a fixed key to increase throughput, achieving a parallel implementation that is 40 times faster but 10 times larger than a serial reference, and a hybrid version that is 8 times faster and twice as large.
In this paper, we explore new area/throughput trade- offs for the Girault, Poupard and Stern authentication protocol (GPS). This authentication protocol was selected in the NESSIE competition and is even part of the standard ISO/IEC 9798. The originality of our work comes from the fact that we exploit a fixed key to increase the throughput. It leads us to implement GPS using the Chapman constant multiplier. This parallel implementation is 40 times faster but 10 times bigger than the reference serial one. We propose to serialize this multiplier to reduce its area at the cost of lower throughput. Our hybrid Chapman's multiplier is 8 times faster but only twice bigger than the reference. Results presented here allow designers to adapt the performance of GPS authentication to their hardware resources. The complete GPS prover side is also integrated in the network stack of the PowWow sensor which contains an Actel IGLOO AGL250 FPGA as a proof of concept.