Multiplierless Approximate 4-point DCT VLSI Architectures for Transform Block Coding
This work addresses power efficiency for digital video processing, but it is incremental as it builds on existing DCT methods with hardware optimizations.
The paper tackled the problem of high power consumption in transform block coding for digital video by proposing two multiplierless algorithms for 4x4 approximate-DCT, resulting in real-time operation at 1 GHz with 125 MHz block rates and less than 120 mW dynamic power consumption.
Two multiplierless algorithms are proposed for 4x4 approximate-DCT for transform coding in digital video. Computational architectures for 1-D/2-D realisations are implemented using Xilinx FPGA devices. CMOS synthesis at the 45 nm node indicate real-time operation at 1 GHz yielding 4x4 block rates of 125 MHz at less than 120 mW of dynamic power consumption.