Formal and Informal Methods for Multi-Core Design Space Exploration
This work addresses design-space exploration for embedded systems developers, but it appears incremental as it extends existing formal verification methods.
The paper tackles the problem of design-space exploration for embedded systems by proposing a tool-supported methodology that models applications and multi-processor architectures to evaluate deployment strategies under uncertainty, aiming to enhance the viability of the domain through extended formal verification.
We propose a tool-supported methodology for design-space exploration for embedded systems. It provides means to define high-level models of applications and multi-processor architectures and evaluate the performance of different deployment (mapping, scheduling) strategies while taking uncertainty into account. We argue that this extension of the scope of formal verification is important for the viability of the domain.