Physical Computing With No Clock to Implement the Gaussian Pyramid of SIFT Algorithm
This provides a high-speed, energy-efficient solution for image processing tasks, though it is incremental as it focuses on optimizing a specific stage of an existing algorithm.
The paper tackles the problem of accelerating the Gaussian pyramid stage in the SIFT algorithm for image feature extraction by proposing a physical computing technology using an active circuit network, achieving processing times at the nanosecond level and power consumption of around 670pJ for a 256x256 image.
Physical computing is a technology utilizing the nature of electronic devices and circuit topology to cope with computing tasks. In this paper, we propose an active circuit network to implement multi-scale Gaussian filter, which is also called Gaussian Pyramid in image preprocessing. Various kinds of methods have been tried to accelerate the key stage in image feature extracting algorithm these years. Compared with existing technologies, GPU parallel computing and FPGA accelerating technology, physical computing has great advantage on processing speed as well as power consumption. We have verified that processing time to implement the Gaussian pyramid of the SIFT algorithm stands on nanosecond level through the physical computing technology, while other existing methods all need at least hundreds of millisecond. With an estimate on the stray capacitance of the circuit, the power consumption is around 670pJ to filter a 256x256 image. To the best of our knowledge, this is the most fast processing technology to accelerate the SIFT algorithm, and it is also a rather energy-efficient method, thanks to the proposed physical computing technology.