Mitigating Hardware Cyber-Security Risks in Error Correcting Decoders
This addresses security vulnerabilities in semiconductor hardware for industries relying on channel decoders, but it is incremental as it builds on existing risk mitigation approaches.
The paper tackles the problem of hardware cyber-security risks in channel decoders, which are vulnerable to malicious attacks, and proposes methods to mitigate these risks by randomizing inputs without affecting decoding performance.
This paper investigates hardware cyber-security risks associated with channel decoders, which are commonly acquired as a black box in semiconductor industry. It is shown that channel decoders are potentially attractive targets for hardware cyber-security attacks and can be easily embedded with malicious blocks. Several attack scenarios are considered in this work and suitable methods for mitigating the risks are proposed. These methods are based on randomizing the inputs of the channel decoder to obstruct the communications between attackers and the malicious blocks, ideally without changing the decoding performance.