A Holistic Approach in Embedded System Development
This addresses validation inefficiencies for embedded system engineers, but appears incremental as it builds on existing hierarchical state machine methods.
The authors tackled the problem of reducing validation time in embedded system development by introducing pState, a tool that integrates validation into the design process, resulting in executable code that preserves verified properties without requiring engineers to know temporal logic.
We present pState, a tool for developing "complex" embedded systems by integrating validation into the design process. The goal is to reduce validation time. To this end, qualitative and quantitative properties are specified in system models expressed as pCharts, an extended version of hierarchical state machines. These properties are specified in an intuitive way such that they can be written by engineers who are domain experts, without needing to be familiar with temporal logic. From the system model, executable code that preserves the verified properties is generated. The design is documented on the model and the documentation is passed as comments into the generated code. On the series of examples we illustrate how models and properties are specified using pState.