OpenCL 2.0 for FPGAs using OCLAcc
This addresses the challenge of hardware design complexity for developers of embedded and high-performance applications, offering an incremental improvement by leveraging OpenCL 2.0 features.
The authors tackled the problem of time-consuming and complex hardware design by presenting OCLAcc, a tool that generates FPGA-based hardware accelerators from OpenCL, enabling higher-level abstraction to reduce development time and allow iterative testing and optimization.
Designing hardware is a time-consuming and complex process. Realization of both, embedded and high-performance applications can benefit from a design process on a higher level of abstraction. This helps to reduce development time and allows to iteratively test and optimize the hardware design during development, as common in software development. We present our tool, OCLAcc, which allows the generation of entire FPGA-based hardware accelerators from OpenCL and discuss the major novelties of OpenCL 2.0 and how they can be realized in hardware using OCLAcc.