Applying Multi-Core Model Checking to Hardware-Software Partitioning in Embedded Systems (extended version)
This work addresses partitioning challenges for embedded systems designers, but it appears incremental as it applies existing multi-core techniques to a specific domain problem.
The paper tackles the hardware-software partitioning problem in embedded systems by proposing a multi-core SMT-based bounded model checking approach, achieving effectiveness in finding optimal solutions compared to Integer Linear Programming and Genetic Algorithm methods.
We present an alternative approach to solve the hardware (HW) and software (SW) partitioning problem, which uses Bounded Model Checking (BMC) based on Satisfiability Modulo Theories (SMT) in conjunction with a multi-core support using Open Multi-Processing. The multi-core SMT-based BMC approach allows initializing many verification instances based on processors cores numbers available to the model checker. Each instance checks for a different optimum value until the optimization problem is satisfied. The goal is to show that multi-core model-checking techniques can be effective, in particular cases, to find the optimal solution of the HW-SW partitioning problem using an SMT-based BMC approach. We compare the experimental results of our proposed approach with Integer Linear Programming and the Genetic Algorithm.