Memory-Efficient Design Strategy for a Parallel Embedded Integral Image Computation Engine
This work addresses memory constraints in embedded vision systems, offering an incremental improvement for hardware design.
The paper tackled the problem of high memory requirements in parallel integral image computation for embedded vision systems by proposing a memory-efficient design strategy, achieving nearly 35% reduction in memory for HD video.
In embedded vision systems, parallel computation of the integral image presents several design challenges in terms of hardware resources, speed and power consumption. Although recursive equations significantly reduce the number of operations for computing the integral image, the required internal memory becomes prohibitively large for an embedded integral image computation engine for increasing image sizes. With the objective of achieving high-throughput with minimum hardware resources, this paper proposes a memory-efficient design strategy for a parallel embedded integral image computation engine. Results show that the design achieves nearly 35% reduction in memory for common HD video.