A New Learning Method for Inference Accuracy, Core Occupation, and Performance Co-optimization on TrueNorth Chip
This addresses a hardware-specific bottleneck for neuromorphic computing researchers and engineers, offering a significant improvement over existing workarounds.
The paper tackles the problem of low inference accuracy on the IBM TrueNorth neuromorphic chip due to low quantization resolution, by proposing a novel learning method that reduces the number of computation copies needed. The result is up to 68.8% reduction in required neuro-synaptic cores or 6.5X speedup, with slightly improved accuracy.
IBM TrueNorth chip uses digital spikes to perform neuromorphic computing and achieves ultrahigh execution parallelism and power efficiency. However, in TrueNorth chip, low quantization resolution of the synaptic weights and spikes significantly limits the inference (e.g., classification) accuracy of the deployed neural network model. Existing workaround, i.e., averaging the results over multiple copies instantiated in spatial and temporal domains, rapidly exhausts the hardware resources and slows down the computation. In this work, we propose a novel learning method on TrueNorth platform that constrains the random variance of each computation copy and reduces the number of needed copies. Compared to the existing learning method, our method can achieve up to 68.8% reduction of the required neuro-synaptic cores or 6.5X speedup, with even slightly improved inference accuracy.