VLSI Extreme Learning Machine: A Design Space Exploration
This addresses the problem of computational intensity and physical limits in hardware machine learning for embedded or low-power applications, though it is incremental as it builds on existing ELM methods.
The paper tackles the hardware implementation of an extreme learning machine (ELM) by designing a compact, low-power chip using current mirror mismatches for vector-matrix multiplication, achieving an energy efficiency of 0.47 pJ/MAC at 31.6 kHz classification rate.
In this paper, we describe a compact low-power, high performance hardware implementation of the extreme learning machine (ELM) for machine learning applications. Mismatch in current mirrors are used to perform the vector-matrix multiplication that forms the first stage of this classifier and is the most computationally intensive. Both regression and classification (on UCI data sets) are demonstrated and a design space trade-off between speed, power and accuracy is explored. Our results indicate that for a wide set of problems, $σV_T$ in the range of $15-25$mV gives optimal results. An input weight matrix rotation method to extend the input dimension and hidden layer size beyond the physical limits imposed by the chip is also described. This allows us to overcome a major limit imposed on most hardware machine learners. The chip is implemented in a $0.35 μ$m CMOS process and occupies a die area of around 5 mm $\times$ 5 mm. Operating from a $1$ V power supply, it achieves an energy efficiency of $0.47$ pJ/MAC at a classification rate of $31.6$ kHz.