FPGA Design for Pseudorandom Number Generator Based on Chaotic Iteration used in Information Hiding Application
This work addresses the need for faster and secure random number generation in information hiding applications, but it is incremental as it builds on prior research by optimizing an existing method for hardware implementation.
The paper tackles the bottleneck of inefficient random number generation in information communication by redesigning a chaotic iteration-based pseudorandom number generator for FPGA devices, resulting in a largely improved generation rate and demonstrating good statistical and cryptographic security properties.
Lots of researches indicate that the inefficient generation of random numbers is a significant bottleneck for information communication applications. Therefore, Field Programmable Gate Array (FPGA) is developed to process a scalable fixed-point method for random streams generation. In our previous researches, we have proposed a technique by applying some well-defined discrete chaotic iterations that satisfy the reputed Devaney's definition of chaos, namely chaotic iterations (CI). We have formerly proven that the generator with CI can provide qualified chaotic random numbers. In this paper, this generator based on chaotic iterations is optimally redesigned for FPGA device. By doing so, the generation rate can be largely improved. Analyses show that these hardware generators can also provide good statistical chaotic random bits and can be cryptographically secure too. An application in the information hiding security field is finally given as an illustrative example.