FINN: A Framework for Fast, Scalable Binarized Neural Network Inference
This work addresses the need for efficient, low-power neural network inference on embedded systems, offering a novel hardware optimization approach.
The paper tackles the problem of accelerating binarized neural network inference by presenting FINN, a framework for building fast FPGA accelerators, achieving up to 12.3 million classifications per second on MNIST with 95.8% accuracy and 21,906 per second on CIFAR-10 with 80.1% accuracy.
Research has shown that convolutional neural networks contain significant redundancy, and high classification accuracy can be obtained even when weights and activations are reduced from floating point to binary values. In this paper, we present FINN, a framework for building fast and flexible FPGA accelerators using a flexible heterogeneous streaming architecture. By utilizing a novel set of optimizations that enable efficient mapping of binarized neural networks to hardware, we implement fully connected, convolutional and pooling layers, with per-layer compute resources being tailored to user-provided throughput requirements. On a ZC706 embedded FPGA platform drawing less than 25 W total system power, we demonstrate up to 12.3 million image classifications per second with 0.31 μs latency on the MNIST dataset with 95.8% accuracy, and 21906 image classifications per second with 283 μs latency on the CIFAR-10 and SVHN datasets with respectively 80.1% and 94.9% accuracy. To the best of our knowledge, ours are the fastest classification rates reported to date on these benchmarks.