Design Automation for Obfuscated Circuits with Multiple Viable Functions
This addresses security for hardware designers against targeted attacks, but is incremental as it builds on existing gate camouflaging techniques.
The paper tackles the problem of obfuscating circuits against reverse engineering when adversaries know the set of viable functions, by proposing a method that ensures no viable function can be ruled out without uncovering camouflaged cells, achieving up to 38% area reduction in PRESENT-style S-boxes and 48% in DES S-boxes.
Gate camouflaging is a technique for obfuscating the function of a circuit against reverse engineering attacks. However, if an adversary has pre-existing knowledge about the set of functions that are viable for an application, random camouflaging of gates will not obfuscate the function well. In this case, the adversary can target their search, and only needs to decide whether each of the viable functions could be implemented by the circuit. In this work, we propose a method for using camouflaged cells to obfuscate a design that has a known set of viable functions. The circuit produced by this method ensures that an adversary will not be able to rule out any viable functions unless she is able to uncover the gate functions of the camouflaged cells. Our method comprises iterated synthesis within an overall optimization loop to combine the viable functions, followed by technology mapping to deploy camouflaged cells while maintaining the plausibility of all viable functions. We evaluate our technique on cryptographic S-box functions and show that, relative to a baseline approach, it achieves up to 38\% area reduction in PRESENT-style S-Boxes and 48\% in DES S-boxes.