Sparse Iterative Learning Control with Application to a Wafer Stage: Achieving Performance, Resource Efficiency, and Task Flexibility
For mechatronics control engineers, this framework offers a principled way to balance performance, resource efficiency, and flexibility in ILC, though the improvements are incremental over existing methods.
The paper develops a general optimization-based Iterative Learning Control (ILC) framework that enforces sparsity via convex relaxations, addressing trial-varying disturbances. Applied to a wafer stage, it achieves resource-efficient implementation and disturbance attenuation while maintaining performance.
Trial-varying disturbances are a key concern in Iterative Learning Control (ILC) and may lead to inefficient and expensive implementations and severe performance deterioration. The aim of this paper is to develop a general framework for optimization-based ILC that allows for enforcing additional structure, including sparsity. The proposed method enforces sparsity in a generalized setting through convex relaxations using $\ell_1$ norms. The proposed ILC framework is applied to the optimization of sampling sequences for resource efficient implementation, trial-varying disturbance attenuation, and basis function selection. The framework has a large potential in control applications such as mechatronics, as is confirmed through an application on a wafer stage.