ShiftCNN: Generalized Low-Precision Architecture for Inference of Convolutional Neural Networks
This work addresses the need for efficient inference accelerators in custom hardware like FPGAs or ASICs, offering a multiplierless approach that is incremental but provides substantial gains in power and computational efficiency.
The authors tackled the problem of high computational cost in convolutional neural network inference by introducing ShiftCNN, a low-precision architecture that uses power-of-two weight representation to perform only shift and addition operations, reducing product operations by at least two orders of magnitude and achieving less than 1% accuracy drop on ImageNet with a 4x power reduction in FPGA simulations.
In this paper we introduce ShiftCNN, a generalized low-precision architecture for inference of multiplierless convolutional neural networks (CNNs). ShiftCNN is based on a power-of-two weight representation and, as a result, performs only shift and addition operations. Furthermore, ShiftCNN substantially reduces computational cost of convolutional layers by precomputing convolution terms. Such an optimization can be applied to any CNN architecture with a relatively small codebook of weights and allows to decrease the number of product operations by at least two orders of magnitude. The proposed architecture targets custom inference accelerators and can be realized on FPGAs or ASICs. Extensive evaluation on ImageNet shows that the state-of-the-art CNNs can be converted without retraining into ShiftCNN with less than 1% drop in accuracy when the proposed quantization algorithm is employed. RTL simulations, targeting modern FPGAs, show that power consumption of convolutional layers is reduced by a factor of 4 compared to conventional 8-bit fixed-point architectures.