An Analog Neural Network Computing Engine using CMOS-Compatible Charge-Trap-Transistor (CTT)
This addresses hardware efficiency for neural network inference by reducing area and power compared to digital multipliers, though it's an incremental improvement using existing CTT technology.
The authors developed an analog neural network computing engine using CMOS-compatible charge-trap transistors as analog multipliers, achieving 76.8 TOPS at 8-bit resolution with 14.8 mW power consumption and 0.68mm² area in a 28nm implementation.
An analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed in this paper. CTT devices are used as analog multipliers. Compared to digital multipliers, CTT-based analog multiplier shows significant area and power reduction. The proposed computing engine is composed of a scalable CTT multiplier array and energy efficient analog-digital interfaces. Through implementing the sequential analog fabric (SAF), the engine mixed-signal interfaces are simplified and hardware overhead remains constant regardless of the size of the array. A proof-of-concept 784 by 784 CTT computing engine is implemented using TSMC 28nm CMOS technology and occupied 0.68mm2. The simulated performance achieves 76.8 TOPS (8-bit) with 500 MHz clock frequency and consumes 14.8 mW. As an example, we utilize this computing engine to address a classic pattern recognition problem -- classifying handwritten digits on MNIST database and obtained a performance comparable to state-of-the-art fully connected neural networks using 8-bit fixed-point resolution.