Reverse Engineering Camouflaged Sequential Integrated Circuits Without Scan Access
This work addresses a security vulnerability in chip design protection for hardware engineers, showing that restricting scan access does not guarantee security, representing a significant advance over prior attacks limited to combinational circuits.
The paper tackles the problem of reverse engineering camouflaged sequential integrated circuits without scan access, developing a new attack methodology using a model checker to find discriminating input sequences, which successfully decamouflages a large sequential benchmark circuit implementing a subset of the VIPER processor.
Integrated circuit (IC) camouflaging is a promising technique to protect the design of a chip from reverse engineering. However, recent work has shown that even camouflaged ICs can be reverse engineered from the observed input/output behaviour of a chip using SAT solvers. However, these so-called SAT attacks have so far targeted only camouflaged combinational circuits. For camouflaged sequential circuits, the SAT attack requires that the internal state of the circuit is controllable and observable via the scan chain. It has been implicitly assumed that restricting scan chain access increases the security of camouflaged ICs from reverse engineering attacks. In this paper, we develop a new attack methodology to decamouflage sequential circuits without scan access. Our attack uses a model checker (a more powerful reasoning tool than a SAT solver) to find a discriminating set of input sequences, i.e., one that is sufficient to determine the functionality of camouflaged gates. We propose several refinements, including the use of a bounded model checker, and sufficient conditions for determining when a set of input sequences is discriminating to improve the run-time and scalabilty of our attack. Our attack is able to decamouflage a large sequential benchmark circuit that implements a subset of the VIPER processor.