Interleaver Design for Deep Neural Networks
This work addresses efficiency issues in DNNs for hardware and AI applications, but it appears incremental as it builds on existing sparsity and interleaving concepts.
The paper tackles the problem of high memory and computational demands in deep neural networks by proposing a class of interleavers that use structured sparsity to lower these requirements and speed up training, with guarantees for clash-free memory accesses and optimized network performance.
We propose a class of interleavers for a novel deep neural network (DNN) architecture that uses algorithmically pre-determined, structured sparsity to significantly lower memory and computational requirements, and speed up training. The interleavers guarantee clash-free memory accesses to eliminate idle operational cycles, optimize spread and dispersion to improve network performance, and are designed to ease the complexity of memory address computations in hardware. We present a design algorithm with mathematical proofs for these properties. We also explore interleaver variations and analyze the behavior of neural networks as a function of interleaver metrics.