A Hardware-Friendly Algorithm for Scalable Training and Deployment of Dimensionality Reduction Models on FPGA
This work addresses the problem of efficient hardware design for machine learning training and deployment, particularly for dimensionality reduction models, offering a scalable solution that is incremental in improving existing methods.
The paper tackled the challenge of training and deploying dimensionality reduction models on hardware by introducing a hardware-friendly algorithm, resulting in a 50% reduction in resource consumption without accuracy loss compared to state-of-the-art implementations.
With ever-increasing application of machine learning models in various domains such as image classification, speech recognition and synthesis, and health care, designing efficient hardware for these models has gained a lot of popularity. While the majority of researches in this area focus on efficient deployment of machine learning models (a.k.a inference), this work concentrates on challenges of training these models in hardware. In particular, this paper presents a high-performance, scalable, reconfigurable solution for both training and deployment of different dimensionality reduction models in hardware by introducing a hardware-friendly algorithm. Compared to state-of-the-art implementations, our proposed algorithm and its hardware realization decrease resource consumption by 50\% without any degradation in accuracy.