LGARMLFeb 2, 2018

VIBNN: Hardware Acceleration of Bayesian Neural Networks

arXiv:1802.00822v198 citations
Originality Incremental advance
AI Analysis

This addresses the high hardware cost problem for implementing BNNs in practical applications, though it is incremental as it builds on existing BNN methods with hardware optimizations.

The paper tackles the hardware implementation challenge of Bayesian Neural Networks (BNNs) by proposing VIBNN, an FPGA-based accelerator that introduces two optimized Gaussian random number generators and a pipelined architecture, achieving throughput of 321,543.4 images/s and energy efficiency up to 52,694.8 images/J while maintaining accuracy comparable to software.

Bayesian Neural Networks (BNNs) have been proposed to address the problem of model uncertainty in training and inference. By introducing weights associated with conditioned probability distributions, BNNs are capable of resolving the overfitting issue commonly seen in conventional neural networks and allow for small-data training, through the variational inference process. Frequent usage of Gaussian random variables in this process requires a properly optimized Gaussian Random Number Generator (GRNG). The high hardware cost of conventional GRNG makes the hardware implementation of BNNs challenging. In this paper, we propose VIBNN, an FPGA-based hardware accelerator design for variational inference on BNNs. We explore the design space for massive amount of Gaussian variable sampling tasks in BNNs. Specifically, we introduce two high performance Gaussian (pseudo) random number generators: the RAM-based Linear Feedback Gaussian Random Number Generator (RLF-GRNG), which is inspired by the properties of binomial distribution and linear feedback logics; and the Bayesian Neural Network-oriented Wallace Gaussian Random Number Generator. To achieve high scalability and efficient memory access, we propose a deep pipelined accelerator architecture with fast execution and good hardware utilization. Experimental results demonstrate that the proposed VIBNN implementations on an FPGA can achieve throughput of 321,543.4 Images/s and energy efficiency upto 52,694.8 Images/J while maintaining similar accuracy as its software counterpart.

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