Power efficient Spiking Neural Network Classifier based on memristive crossbar network for spike sorting application
This work addresses the need for energy-efficient neural signal processing in brain-machine interfaces, though it appears incremental as it builds on existing SNN and memristive methods.
The authors tackled the problem of low-power spike sorting for implantable biomedical systems by proposing a two-step shared training scheme using K-means and a Spiking Neural Network (SNN) with a memristive crossbar architecture, achieving comparable accuracy to digital implementations while being power-efficient.
In this paper authors have presented a power efficient scheme for implementing a spike sorting module. Spike sorting is an important application in the field of neural signal acquisition for implantable biomedical systems whose function is to map the Neural-spikes (N-spikes) correctly to the neurons from which it originates. The accurate classification is a pre-requisite for the succeeding systems needed in Brain-Machine-Interfaces (BMIs) to give better performance. The primary design constraint to be satisfied for the spike sorter module is low power with good accuracy. There lies a trade-off in terms of power consumption between the on-chip and off-chip training of the N-spike features. In the former case care has to be taken to make the computational units power efficient whereas in the later the data rate of wireless transmission should be minimized to reduce the power consumption due to the transceivers. In this work a 2-step shared training scheme involving a K-means sorter and a Spiking Neural Network (SNN) is elaborated for on-chip training and classification. Also, a low power SNN classifier scheme using memristive crossbar type architecture is compared with a fully digital implementation. The advantage of the former classifier is that it is power efficient while providing comparable accuracy as that of the digital implementation due to the robustness of the SNN training algorithm which has a good tolerance for variation in memristance.